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Figure 1 – (a) Schematic of the 3-word-line based 3D CCD structure: bottom gate (BG), center gate (CG), and top gate (TG), with source (S) at the bottom and drain (D) at the top; (b) cross-sectional TEM image showing 3 gate layers with a word-line pitch of 80nm. Figure 2 – (a) Illustration of the pulsing scheme across 3 gates for serial charge transfer in a 3-word-line based 3D CCD memory; (b) Schematic of 3D CCD operation showing electron transfer through the formation and shifting of potential wells under the gates. Figure 3 – (a) I-f characteristics from 7 devices with varying memory hole (MH) diameters, measured up to 4MHz; (b) the number of electrons transferred per cycle obtained from the slope of the corresponding I-f curves.
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  • Electronics (wafers, semiconductors, microchips,...)

The feasibility of processing a charge coupled device (CCD) in a 3D NAND-like architecture paves the way for a cost-effective, high-bit-density memory solution to address the memory wall for AI specific workloads

Imec demonstrates the first 3D implementation of a charge coupled device for AI memory applications

– Imec presents the first 3D implementation of a charge coupled device (CCD) with indium-gallium-zinc-oxide (IGZO) channel, with potential for AI memory applications.
– Due to the cost-effective fabrication, high bit density, and block-addressable nature, the 3D CCD device shows promise to be used a…
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  • Electronics (wafers, semiconductors, microchips,...)

Expands global ASIC services expertise and aims to take on the industry’s most advanced AI, HPC, mobile and automotive projects

IC-Link by imec joins TSMC 3DFabric® Alliance to accelerate advanced packaging and 3D IC innovation

Imec, a world-leading research and innovation hub in advanced semiconductor technologies, announced that IC-Link by imec, imec’s design and manufacturing service provider for ASIC and silicon photonics, has joined TSMC Open Innovation Platform® (OIP) 3DFabric® Alliance. As part of the TSMC OIP e…
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  • Electronics (wafers, semiconductors, microchips,...)

A major milestone in propelling industry into the ångström era

Imec receives the world’s most advanced High NA EUV system

– Imec announces the arrival of the ASML EXE:5200, the world’s most advanced High NA EUV lithography system, in its 300mm cleanroom in Leuven. 
– Operating the High NA EUV system in direct connection with state-of-the-art metrology and patterning equipment/materials accelerates learning cycles to unlo…
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  • Electronics (wafers, semiconductors, microchips,...)

New advanced interconnect PDKs pave the way for high‑density, energy‑efficient chip‑to‑chip integration.

NanoIC opens access to first-ever fine-pitch RDL and D2W hybrid bonding interconnect PDKs

On 2nd March 2026 the NanoIC pilot line, a European initiative coordinated by imec and dedicated to accelerating innovation in chip technologies beyond 2nm, released two first-of-a-kind advanced interconnect process design kits (PDKs): a fine-pitch redistribution layer (RDL) and die-to-wafer (D2W) h…
Left to Right: Patrick Vandenameele (CEO-elect imec), Thomas Skordas (European Commissioner), Luc Van den hove (CEO imec), Henna Virkkunen (European Commissioner), Matthias Diependaele (MP Flanders), Jari Kinaret (Executive Director Chips JU), Christophe Fouquet (CEO ASML).
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  • New building

Imec celebrates Europe's NanoIC pilot line with the official opening of a 2,000 m² large cleanroom extension on its campus in Leuven.

Imec inaugurates NanoIC pilot line, accelerating innovation in sub-2nm systems-on-chip

– Imec inaugurates Europe’s NanoIC pilot line with the official opening of a 2,000m² cleanroom expansion at its Leuven campus.
– Equipped with cutting-edge tools, including ASML’s High NA EUV tool, imec’s cleanroom is a cornerstone of the NanoIC initiative – pursuing sub-2nm chip technology.
– Exactly four…
3D representation of the A14 device structure showing the 4 stacked nanosheets with its local routing and back side metal contact. A 4x4 IGZO 2T0C cell array where the read/write transistors (RTX/WTX) are located on the top/bottom levels with the corresponding connections.
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  • Electronics (wafers, semiconductors, microchips,...)

Launch of new A14 and embedded DRAM process design kits (PDKs) accelerates research and innovation in logic and memory scaling

NanoIC extends its PDK portfolio with first A14 logic and eDRAM memory PDK

On 2nd February, 2026, the NanoIC pilot line, a European initiative coordinated by imec and dedicated to accelerating innovation in chip technologies beyond 2nm, announced the release of two new process design kits (PDKs): an A14 pathfinding PDK for advanced logic scaling and an eDRAM system explora…
Photos of the Veeco 300-mm oxide system for hybrid-MBE BTO on Silicon epitaxy. Cross-sectional Transmission Electron Microscopy image of the BaTiO₃/SrTiO₃/Si(001) heterostructure with high-resolution micrograph and atomic force microscopy images in inset.
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  • Electronics (wafers, semiconductors, microchips,...)

First-Of-Its-Kind Solution For Barium Titanate Epitaxy on Silicon to Accelerate Datacom and Quantum Computing Applications.

Veeco and imec develop 300mm compatible process to enable integration of barium titanate on silicon photonics

Veeco Instruments Inc. (Nasdaq: VECO) and imec announced today that they have collaboratively developed a 300mm high volume manufacturing compatible process that enables the integration of barium titanate (BaTiO3 or BTO) on a silicon photonics platform. BTO is a promising material with unique electr…
The cleanroom at Imec forms the basis for NanoIC's PDKs, which are based on 2-nm process flows. (Image: Imec) / Imec's cleanroom provides the foundation for NanoIC's PDKs, based on 2 nm process flows. (Photo: Imec)
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  • Workshop / Course

Major update of NanoIC’s Pathfinding N2 P-PDK empowers researchers and designers to learn and innovate on full SoC architectures

NanoIC adds advanced SRAM memory macros to its N2 pathfinding PDK

NanoIC pilot line, a European initiative coordinated by imec and dedicated to accelerating innovation in chip technologies beyond 2nm, announces the release of the N2 P-PDK v1.0, an important update of its N2 Pathfinding Process Design Kit (P-PDK). This new version introduces several new features, i…
Figure 1 – (Left) Transfer curves of 2D-pFET devices using defect-passivated synthetically-created bi-layer WSe2 films, with the best device showing Imax = 690µA/µm; (Right) TEM cross-section of the finalized dual-gated 2D pFET (Lch=channel length; TG=Top Gate; BG=Back Gate; S=Source; D=Drain; IL=Interlayer), in collaboration with TSMC. Figure 2 – (a) Dry etching into SiO₂; (b) Dry and wet etching, which stops selectively on the WS₂ monolayer channel, also removing the AlOx interlayer laterally along the entire channel length (in collaboration with Intel).
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  • Electronics (wafers, semiconductors, microchips,...)

Collaboration with leading semiconductor manufacturers pivotal in optimizing the key modules for 2D-material device integration

Imec advances 2D-material based device technology beyond state of the art in support of the future logic technology roadmap

– Imec, in collaboration with leading semiconductor manufacturers, addressed key challenges in advancing 2D-material device technology, which is considered a long-term option for extending the logic technology roadmap.
– Collaboration with TSMC resulted in record performing WSe2 -based pFETs (with I…
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