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Figure 1 – Schematic comparison of (left) conventional via-middle and (right) local-BDI TSV approaches, assuming a cell height of 115nm and bulk Si thickness of 500nm. Figure 2 – Overlay dependence of the chain resistance of TSV/MOL-via structures, showing 30nm overlay window. The solid black line represents simulations; dashed lines represent ±5% CD.
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  • Electronics (wafers, semiconductors, microchips,...)

The new integration approach implements sub-100nm self-aligned through-Si via connections, enabling low-resistance and low-leakage front-to-back connections with good overlay performance.

Sony and imec unveil high-density backside connectivity module enabling next-generation 3D chip integration

– Sony and imec introduce a novel module for integrating highly dense backside sub-100nm through-Si vias (TSVs), based on a self-aligned local backside dielectric isolation (local BDI) step.
– The resulting front-to-back TSVs have lower aspect ratio, 3x lower resistance, 3x larger overlay window, and…
Figure 1 - (A) X-cut HAADF STEM for a WS2 device with a CPP of 50nm, a contact length of 19nm and width of 256nm, after gate connection line etch. And (B) corresponding energy dispersive X-ray spectroscopy (EDS) EDS analysis. Figure 2 – MoS2 nFETs and WSe2 pFETs with 50nm contact pitch and relaxed channel width (650nm), integrated on the same 300mm wafer, show proper threshold voltage matching.
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  • Electronics (wafers, semiconductors, microchips,...)

Novel 300mm integration approach for 2D-material based devices enables scaled n and pFETs with 50nm contacted poly pitch.

ASML, TSMC and imec bring industry-ready 2D-material transistors closer with breakthrough 300mm integration

– ASML, TSMC, and imec introduce an innovative 300-mm integration process for transistors based on 2D materials, enabling the first scalable n- and p-FETs with a contact pitch (CPP) of 50 nm, structured using EUV lithography.
– Good results were achieved with scaled nFETs (with MoS2 channel) and pFET…
High-density MIMCAP in a 300mm silicon interposer High-density MIMCAP in a 300mm silicon interposer
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  • Electronics (wafers, semiconductors, microchips,...)

Imec unlocks system-level III-V chiplet integration on Si-CMOS by advancing its 300mm RF silicon interposer platform with high-density MIMCAPs, passive modeling, and laser-assisted bonding

– Imec is evolving its 300mm RF silicon interposer into a unique, system-level platform for the heterogeneous integration of III‑V chiplets on Si‑CMOS – targeting mmWave/sub‑THz wireless and high‑speed data center applications.
– A new MIMCAP architecture delivers a 10-to-100-fold increase in capacit…
Functioning array of qubits with gaps between plunger (P) and barrier (B) gates of barely 6 nanometers, enabled by High NA EUV lithography. The image also shows the accumulation gates (A) and confinement (C).
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  • Electronics (wafers, semiconductors, microchips,...)

The most advanced lithography system, crucial for future advanced memory and computer chips, will play a key role in scaling up quantum technology.

World first: imec presents quantum dot qubit device using High NA EUV lithography

    1. Imec presents a world first: a quantum dot qubit device fabricated using High NA EUV lithography.   
2. This demonstration marks a milestone toward the industrial scaling of more reliable qubits, the basic computational units of quantum computers. Quantum computers will perform exponentially bette…
Figure 1 – (a) Schematic of the 3-word-line based 3D CCD structure: bottom gate (BG), center gate (CG), and top gate (TG), with source (S) at the bottom and drain (D) at the top; (b) cross-sectional TEM image showing 3 gate layers with a word-line pitch of 80nm. Figure 2 – (a) Illustration of the pulsing scheme across 3 gates for serial charge transfer in a 3-word-line based 3D CCD memory; (b) Schematic of 3D CCD operation showing electron transfer through the formation and shifting of potential wells under the gates. Figure 3 – (a) I-f characteristics from 7 devices with varying memory hole (MH) diameters, measured up to 4MHz; (b) the number of electrons transferred per cycle obtained from the slope of the corresponding I-f curves.
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  • Electronics (wafers, semiconductors, microchips,...)

The feasibility of processing a charge coupled device (CCD) in a 3D NAND-like architecture paves the way for a cost-effective, high-bit-density memory solution to address the memory wall for AI specific workloads

Imec demonstrates the first 3D implementation of a charge coupled device for AI memory applications

– Imec presents the first 3D implementation of a charge coupled device (CCD) with indium-gallium-zinc-oxide (IGZO) channel, with potential for AI memory applications.
– Due to the cost-effective fabrication, high bit density, and block-addressable nature, the 3D CCD device shows promise to be used as…
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  • Electronics (wafers, semiconductors, microchips,...)

Expands global ASIC services expertise and aims to take on the industry’s most advanced AI, HPC, mobile and automotive projects

IC-Link by imec joins TSMC 3DFabric® Alliance to accelerate advanced packaging and 3D IC innovation

Imec, a world-leading research and innovation hub in advanced semiconductor technologies, announced that IC-Link by imec, imec’s design and manufacturing service provider for ASIC and silicon photonics, has joined TSMC Open Innovation Platform® (OIP) 3DFabric® Alliance. As part of the TSMC OIP ecosy…
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  • Electronics (wafers, semiconductors, microchips,...)

A major milestone in propelling industry into the ångström era

Imec receives the world’s most advanced High NA EUV system

– Imec announces the arrival of the ASML EXE:5200, the world’s most advanced High NA EUV lithography system, in its 300mm cleanroom in Leuven. 
– Operating the High NA EUV system in direct connection with state-of-the-art metrology and patterning equipment/materials accelerates learning cycles to unl…
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  • Electronics (wafers, semiconductors, microchips,...)

New advanced interconnect PDKs pave the way for high‑density, energy‑efficient chip‑to‑chip integration.

NanoIC opens access to first-ever fine-pitch RDL and D2W hybrid bonding interconnect PDKs

On 2nd March 2026 the NanoIC pilot line, a European initiative coordinated by imec and dedicated to accelerating innovation in chip technologies beyond 2nm, released two first-of-a-kind advanced interconnect process design kits (PDKs): a fine-pitch redistribution layer (RDL) and die-to-wafer (D2W) h…
Left to Right: Patrick Vandenameele (CEO-elect imec), Thomas Skordas (European Commissioner), Luc Van den hove (CEO imec), Henna Virkkunen (European Commissioner), Matthias Diependaele (MP Flanders), Jari Kinaret (Executive Director Chips JU), Christophe Fouquet (CEO ASML).
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  • New building

Imec celebrates Europe's NanoIC pilot line with the official opening of a 2,000 m² large cleanroom extension on its campus in Leuven.

Imec inaugurates NanoIC pilot line, accelerating innovation in sub-2nm systems-on-chip

– Imec inaugurates Europe’s NanoIC pilot line with the official opening of a 2,000m² cleanroom expansion at its Leuven campus.
– Equipped with cutting-edge tools, including ASML’s High NA EUV tool, imec’s cleanroom is a cornerstone of the NanoIC initiative – pursuing sub-2nm chip technology.
– Exactly…
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