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The cleanroom at Imec forms the basis for NanoIC's PDKs, which are based on 2-nm process flows. (Image: Imec) / Imec's cleanroom provides the foundation for NanoIC's PDKs, based on 2 nm process flows. (Photo: Imec)
  • Workshop / Course

Major update of NanoIC’s Pathfinding N2 P-PDK empowers researchers and designers to learn and innovate on full SoC architectures

NanoIC adds advanced SRAM memory macros to its N2 pathfinding PDK

NanoIC pilot line, a European initiative coordinated by imec and dedicated to accelerating innovation in chip technologies beyond 2nm, announces the release of the N2 P-PDK v1.0, an important update of its N2 Pathfinding Process Design Kit (P-PDK). This new version introduces several new features, i…

Figure 1 – (Left) Transfer curves of 2D-pFET devices using defect-passivated synthetically-created bi-layer WSe2 films, with the best device showing Imax = 690µA/µm; (Right) TEM cross-section of the finalized dual-gated 2D pFET (Lch=channel length; TG=Top Gate; BG=Back Gate; S=Source; D=Drain; IL=Interlayer), in collaboration with TSMC. Figure 2 – (a) Dry etching into SiO₂; (b) Dry and wet etching, which stops selectively on the WS₂ monolayer channel, also removing the AlOx interlayer laterally along the entire channel length (in collaboration with Intel).
  • Electronics (wafers, semiconductors, microchips,...)

Collaboration with leading semiconductor manufacturers pivotal in optimizing the key modules for 2D-material device integration

Imec advances 2D-material based device technology beyond state of the art in support of the future logic technology roadmap

– Imec, in collaboration with leading semiconductor manufacturers, addressed key challenges in advancing 2D-material device technology, which is considered a long-term option for extending the logic technology roadmap.
– Collaboration with TSMC resulted in record performing WSe2 -based pFETs (with Im…

3 Steps 10 common mistakes
  • Disinfection | procedures, devices, agents, media (Wipers, Swaps,...)

Cleanroom cleaning and disinfection in practice: 10 common mistakes that increase risks – and how to avoid them

10 common mistakes in cleanroom cleaning and disinfection

Wenn es um GMP geht, stehen meist Herstellprozesse, Validierungen oder Qualifizierungen im Mittelpunkt. Die Reinigung taucht in vielen Betrieben eher am Rand auf – als Routineaufgabe, die „mitläuft“.

Aber was denken Sie – wie viele GMP-Abweichungen hängen tatsächlich mit Reinigung zusammen?

Die Antwor…

Imec pioneers full wafer-scale (300mm) production of solid-state nanopores with EUV lithography, as shown in the photo. © imec Cross-sectional and top-view TEM of the fabricated solid-state nanopore. Cross-sectional and top-view TEM of the fabricated solid-state nanopore.
  • Electronics (wafers, semiconductors, microchips,...)

Breakthrough enables scalable, high-precision biosensing applications in life sciences and healthcare

Imec demonstrates first wafer-scale fabrication of solid-state nanopores using EUV lithography

1. Imec has achieved the first successful wafer-scale fabrication of solid-state nanopores using EUV lithography on 300mm wafers. This innovation transforms nanopore technology from a lab-scale concept into a scalable platform for biosensing, genomics and proteomics.
2. Nanopores are hailed as gamech…

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