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All publications for the rubric Electronics (wafers, semiconductors, microchips,...)

Figure 1 – (a) Schematic of the 3-word-line based 3D CCD structure: bottom gate (BG), center gate (CG), and top gate (TG), with source (S) at the bottom and drain (D) at the top; (b) cross-sectional TEM image showing 3 gate layers with a word-line pitch of 80nm. Figure 2 – (a) Illustration of the pulsing scheme across 3 gates for serial charge transfer in a 3-word-line based 3D CCD memory; (b) Schematic of 3D CCD operation showing electron transfer through the formation and shifting of potential wells under the gates. Figure 3 – (a) I-f characteristics from 7 devices with varying memory hole (MH) diameters, measured up to 4MHz; (b) the number of electrons transferred per cycle obtained from the slope of the corresponding I-f curves.
  • Electronics (wafers, semiconductors, microchips,...)

The feasibility of processing a charge coupled device (CCD) in a 3D NAND-like architecture paves the way for a cost-effective, high-bit-density memory solution to address the memory wall for AI specific workloads

Imec demonstrates the first 3D implementation of a charge coupled device for AI memory applications

– Imec presents the first 3D implementation of a charge coupled device (CCD) with indium-gallium-zinc-oxide (IGZO) channel, with potential for AI memory applications.
– Due to the cost-effective fabrication, high bit density, and block-addressable nature, the 3D CCD device shows promise to be used as…

  • Electronics (wafers, semiconductors, microchips,...)

Expands global ASIC services expertise and aims to take on the industry’s most advanced AI, HPC, mobile and automotive projects

IC-Link by imec joins TSMC 3DFabric® Alliance to accelerate advanced packaging and 3D IC innovation

Imec, a world-leading research and innovation hub in advanced semiconductor technologies, announced that IC-Link by imec, imec’s design and manufacturing service provider for ASIC and silicon photonics, has joined TSMC Open Innovation Platform® (OIP) 3DFabric® Alliance. As part of the TSMC OIP ecosy…

(Copyright: Polytec GmbH)
  • Products, devices, systems, plants for applications

Optical wafer-level characterization of MEMS dynamics with automatic wafer map processing, recipe control, and cleanroom integration into fab-controlled workflows.

Fully automated MEMS vibration analysis in cleanroom: Polytec Micro System Analyzer now with ISO-3 certification and script automation

With the Micro System Analyzers (MSA-600, MSA-650 IRIS, MSA-100-3D), Polytec has been addressing contactless characterization of MEMS dynamics and topography for years – from individual dies to wafer-level testing on probe stations. The current expansion combines this optical measurement technology…

  • Electronics (wafers, semiconductors, microchips,...)

A major milestone in propelling industry into the ångström era

Imec receives the world’s most advanced High NA EUV system

– Imec announces the arrival of the ASML EXE:5200, the world’s most advanced High NA EUV lithography system, in its 300mm cleanroom in Leuven. 
– Operating the High NA EUV system in direct connection with state-of-the-art metrology and patterning equipment/materials accelerates learning cycles to unl…

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