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19.01.2020

Evonetix arbeitet mit imec zusammen, um die Produktion der Chip-basierten Technologie für die DNA-Syntheseplattform der dritten Generation zu erweitern

EVONETIX LTD ('Evonetix'), das Unternehmen für synthetische Biologie, das eine Desktop-Plattform für skalierbare, hochauflösende und schnelle Gensynthese entwickelt, gab heute bekannt, dass es eine Partnerschaft mit imec, einem weltweit führenden Forschungs- und Innovationszentrum, das in den Be…

Groundbreaking idea of the NOTICE project is to use a novel stable oxide material as the basis for both the superconductor and topological insulator material. At the epitaxial interface, Majorana fermions – building blocks for fault-tolerant qubits – will be generated.

11.12.2019

Renommierter europäischer ERC-Sonderpreis für Clement Merckling von imec für die Entwicklung fehlertoleranter Qubits vergeben

Imec, eine der weltweit führenden Forschungs- und Innovationszentren für Nanoelektronik und digitale Technologien, gibt heute bekannt, dass der Europäische Forschungsrat Clement Merckling, Abteilungsleiter bei imec, einen Consolidator Grant für die Ausarbeitung seines Projekts NOTICE gewährt hat.

Die bahn…

Benchmark study: imec’s devices with 4nm, 8nm, 12nm HfO2 and 50nm SiO2 have excellent combination of gmmax and SSmin compared to literature.

TEM pictures showing (a) 3 monolayers MoS2 channel, with contact length 13nm and channel length 29nm Transfer characteristics have improved sub-threshold swing (SS) with thinner HfO2.

Transfer characteristics have improved sub-threshold swing (SS) with thinner HfO2.

11.12.2019

2D materials paving the way to extreme scaling for logic and memory transistors

Imec shows excellent performance in ultra-scaled FETs with 2D-material channel

At this year’s IEEE International Electron Devices Meeting (Dec 7-11 2019), imec, a world-leading research and innovation hub in nanoelectronics and digital technologies, reports an in-depth study of scaled transistors with MoS2 and demonstrates best device performance to date for such materials.

MoS2…

Figure 1 – From FinFET to nanosheet (with buried power rails (BPRs)), forksheet and CFET.

Figure 2 – Layout of SRAM half cells for a) FinFET, b) gate-all-around nanosheet and c) forksheet. The forksheet can provide up to 30% scaling of the bit cell height as the p-n space is not governed by gate extension (GE), gate cut (GE) or dummy fin gate tuck (DFGT).

11.12.2019

TCAD simulations of a new forksheet device show 10 percent performance boost and 20 percent cell area reduction compared to gate-all-around nanosheet devices.

Imec presents forksheet device as the ultimate solution to push scaling towards the 2nm technology node

This week, at the 2019 IEEE International Electron Devices Meeting, imec, a world-leading research and innovation hub in nanoelectronics and digital technologies, presents first standard cell simulation results of its forksheet device designed for sub-3nm logic technology nodes. Compared to nanoshee…

miDiagnostics’ research prototype device that can perform a complete blood cell count from only drops of blood. This prototype device is for research use only, not for in diagnostic procedures.

20.11.2019

miDiagnostics’ disposable blood testing device to be evaluated by imec for use in zero gravity environments

Imec Awarded a Grant from NASA to Advance Space Health Diagnostics

Today, imec, a world-leading research and innovation hub in nano-electronics and digital technologies announced it has received NASA funding to test a technology for monitoring astronauts’ health status under zero gravity conditions using a first-of-its-kind disposable diagnostic device developed…

16.01.2014

SCALPEL Project to Develop Scalable Microfluidic Platform that Analyzes and Sorts Single Cells to greatly simplify Cancer Research and Treatment follow up.

Imec’s Liesbet Lagae Awarded Prestigious European Research Council Grant

Imec, a world leading nanoelectronics research center, proudly announces that Prof. Dr. Liesbet Lagae, R&D Manager Life Science Technologies at imec and professor in Nanobio Physics at KU Leuven, has been awarded a Consolidator Grant for her research project SCALPEL* by the European Research Cou…

15.10.2013

New Center will offer the global semiconductor ecosystem crucial patterning knowledge for sub-10nm technologies

ASML and imec launch Advanced Patterning Center

On October 7, ASML and imec announced the next major step in their extensive collaboration, with the launch of the Advanced Patterning Center. Together they plan to tackle upcoming scaling challenges due to the chip industry’s move towards single digit nanometer dimensions. The Center will be loca…

Graph: Etching at cryogenic temperature results in targeted k-value

16.07.2013

New method allows IC manufacturers to reach scaling levels at 20nm and beyond, without compromising speed and device cross-talk

Imec reveals method of damage free cryogenic etching of ultralow-k dielectrics

Imec today announced a cryogenic etching method that protects the surface of porous ultralow-k dielectrics against excessive plasma induced damages.

As semiconductor technology scales below the 20nm node, the capacitance increases between nearby conductive portions of high-density integrated circuits…

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