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All publications from IMEC Belgium

Collaboration between Sarcura and imec aims to develop a silicon photonics-based cytometry solution allowing real-time process control and manipulation of cells.

SARCURA and imec to collaborate on high throughput cytometry solution for automated (T-)cell separation, tackling manufacturing challenges of cell and gene therapies

Sarcura GmbH, an Austrian early-stage technology startup, today announced that it has entered a collaboration with imec, a world-leading research and innovation hub in nanoelectronics and digital technologies to develop a silicon chip-based prototype of a cytometer for automated cell separation brin…

SWIR images for 3 different pixel pitches. The images with the highest resolution could be captured with the smallest (1.82 µm) pixel pitch. The thin-film photodetector was monolithically integrated on a custom Si-CMOS readout circuit. (Source: Imec)

The monolithic integration of the thin-film photodetector with CMOS readout circuitry offers a path to high-throughput wafer-level manufacturing

Imec Presents a Thin-Film Short-Wave-InfraRed Image Sensor with Sub-2µm Pixel Pitch

Imec, a world-leading research and innovation hub in nanoelectronics and digital technologies, presents a prototype high-resolution short-wave-infrared (SWIR) image sensor with record small pixel pitch of 1.82 µm. It is based on a thin-film photodetector that is monolithically integrated on a custom…

The groundbreaking approach will use virus particles in exhaled air for rapid, simple, convenient, and large-scale testing

Imec begins developing a SARS-CoV-2 test to identify positive cases and confirm within less than five minutes whether someone is contagious.

Imec, a globally leading research and innovation center for nanoelectronics and digital technologies, announced that it has begun developing a groundbreaking SARS-CoV-2 test. Unlike current approaches (using blood, saliva, or a nasal-throat swab), the new test will identify SARS-CoV-2 virus particle…

Figure 1 – From FinFET to nanosheet (with buried power rails (BPRs)), forksheet and CFET. Figure 2 – Layout of SRAM half cells for a) FinFET, b) gate-all-around nanosheet, and c) forksheet. The forksheet can provide up to 30% scaling of the bit cell height as the p-n space is not governed by gate extension (GE), gate cut (GC), or dummy fin gate tuck (DFGT).

TCAD simulations of a new forksheet device show 10 percent performance boost and 20 percent cell area reduction compared to gate-all-around nanosheet devices.

Imec presents forksheet device as the ultimate solution to push scaling towards the 2nm technology node

This week, at the 2019 IEEE International Electron Devices Meeting, imec, a world-leading research and innovation hub in nanoelectronics and digital technologies, presents first standard cell simulation results of its forksheet device designed for sub-3nm logic technology nodes. Compared to nanoshee…

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